1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to apparatus and a related procedure, incorporated in the central processing unit of a data processing system, which tests the central processing unit in a manner similar to the actual operation of the system.
2. Description of the Related Art
Referring first to FIG. 1, a data processing system, including the components necessary to understand the features of the present invention, is shown. The central processing unit 10 includes apparatus for performing the processing of data signal groups, typically stored in the main memory unit 13, in accordance with programs stored as instruction signal groups in the main memory unit 13. The system interface unit 11 provides buffer and control functions for signal groups being transferred into or out of the central processing unit 10. In addition to coupling the central processing unit 10 to the main memory unit 13, the system interface unit 11 provides buffer and control functions for signal groups exchanged between user terminals 12, mass storage units 14, communication devices 15 and any other apparatus exchanging signal groups with the central processing unit 10. A console unit 16 is typically coupled to the central processing unit 10 and includes apparatus for initiating operation of the data processing system, for providing selected control functions and for providing apparatus and programs for testing the apparatus of the central processing unit 10. In other data processing systems, the exchange of data with the central processing unit is accomplished over a system bus rather than through a system interface unit 11. The present invention will operate advantageously in both the data processing system bus type architecture and in the data processing system interface unit type architecture.
Referring specifically to the central processing unit 10 of FIG. 1, components thereof that are important in understanding the operation of the present invention are illustrated within the block labeled central processing unit 10. The signal groups, transferred into the central processing unit, are temporarily stored in the cache memory unit 103 until required by the currently executing program. Signal groups from the cache memory unit 103 are transferred to the operand register 102 and, subsequently, to the instruction register 104. The signal group in the instruction register 104 causes one or more signal groups from the operand register 102 to be processed by the execution unit 101. Signals from the instruction register 104 are applied to the control apparatus 106 which controls the processing of the data signal groups as well as transfer signal groups between components. The processed signal group is typically returned to the operand register group 102 and/or the cache memory unit 103. Thereafter, the processed signal group is transferred to the main memory unit 13 or to a user terminal 12 interacting with the central processing unit 10 . Register array 105 is included to permit the central processing unit 10 to interrupt a currently executing procedure, execute a second procedure, e.g., a procedure having a higher priority, and return to the originally executing procedure. In order to return to the originally executing procedure at the point of interruption, the contents of selected registers are saved, i.e., transferred into register array 105, and the contents are returned to the (same) selected registers upon return to the originally executing procedure. As will be clear to those familiar with data processing systems, the foregoing description provides only an outline of the operation of a central processing unit 10. Data paths, control signal paths, associated apparatus, etc. have all been omitted although such apparatus is essential to the operation of central processing unit 10. In the preferred embodiment, the execution unit 101 has a pipelined configuration and is implemented using the techniques of microprogrammed control. In FIG. 1, the microprocessor control apparatus is designated as control apparatus 106. However, as will be clear, the microprogramming implementation as well as the pipelining techniques are not required for advantageous use of the present invention.
The complexity of the central processing unit 10 provides an enormous opportunity for malfunction. In order to verify the operation the central processing units, numerous procedure checking techniques, such as parity checking apparatus, can be incorporated in the central processing unit 10. Verification programs that are designed to check the operation of the central processing unit 10 can be stored in the main memory unit 13 or in the console unit 14. These verification programs are designed to exercise all the components of the central processing unit 10 and to provide processing results that can be compared with results known to be accurate. The verification programs are initiated in response to a detected error or in response to a maintenance strategy. The verification programs are lengthy and, in the event an error has not been detected, can occupy unacceptable amount of processing time when used as an operation verification mechanism. Part of the reason for the length of the verification program is that, for some programs, a portion of the central processing unit is exercised and the results compared against expected results. This type of program frequently executes a procedure for one or a few number of clock cycles in order to prevent confusion in the diagnostic procedures resulting from fan-out of errors. None-the-less, execution of verification programs is essential because many types of malfunctions do not produce detectable errors while still resulting in erroneous results.
More recently, a technique has been developed for testing the apparatus of a central processing unit that is known as non-functional or native fault testing (along with a multiplicity of other designations). In this technique, in response to control signals, typically from the console unit 14, the registers of the central processing unit are reconfigured into a single or relatively small number of shift registers. In this configuration, the contents of the shift register(s) can be shifted out of the central processing unit and the logic signal(s) in any predetermined register position (or positions) identified. Similarly, all the register positions of the central processing unit can have known signals entered therein (by means of the shift register configuration). Therefore, the initial state of the central processing unit can be determined and the resulting state, after a selected number of machine clock cycles, can be determined, thereby providing an operator with the ability to test the operation of the central processing unit at the gate level. This technique can interrupt the operation of the central processing unit for a relatively long period of time and does not truly exercise the central processing unit in the way that the central processing unit performs the processing functions.
A need has therefore been felt for apparatus and an associated technique that can verify the operation of a central processing unit in the manner in which the central processing unit is typically operated, while having a minimum impact of the availability of the central processing unit to execute user tasks. In addition, the test procedure should be capable of exercising the cache memory unit, an area of the central processing unit frequently overlooked by the test procedures currently available.